1. Field of Invention
The present invention relates to a tri-state output buffer of the type that includes a totem-pole or series arrangement of a pair of bipolar output transistors. More particularly, this invention pertains to a circuit for protecting the base-emitter junction of the source-follower from harmful levels of reverse bias and for preventing conduction when the buffer is disabled.
2. Description of the prior art
The operation of tri-state logic requires a high impedance or "disabled" state in addition to the "high" and "low" levels of binary logic. As a consequence, the output can occasionally "float". This can lead to serious problems for certain circuit topologies.
A conventional bipolar tri-state buffer can include a dual transistor push-pull output driver stage with a first bipolar transistor coupled between a d.c. voltage supply and an output load and a second bipolar transistor of the same type coupled between the output load and ground. The output stage of a conventional tri-state buffer of this type is illustrated in the schematic diagram of FIG. 1. In operation, a high voltage state is realized at the output node 10 by turning on a first source-follower bipolar transistor 12 and turning off a second output transistor 14. A low output state is realized by turning off the first bipolar transistor 12 and turning on the second transistor 14. A high impedance is achieved at the output node 10 by turning off both transistors (disabled state). As mentioned earlier, the output node 10 effectively floats when the buffer is not enabled. Normally, in a tri-state buffer of the type shown in FIG. 1, the bases of the transistors 12 and 14 are tied to ground in the disabled state. The node 10 is driven to the high state by tying the base of the transistor 12 high and that of the transistor 14 low and vice versa.
External I/0 driver circuitry 16 is, of course, generally coupled to the output node 10 which is also coupled to the emitter terminal of the source-follower transistor 12. The driver 16 is represented by a switch or gate whose state depends upon whether the driver 16 is operative in a "transmitter" or "receiver" mode and a capacitor 16' that represents the capacitance of the conductor that connects the node 10 to the driver 16. The presence of the capacitor 16'makes the switching transition time at the node 10 longer than that at the base of the bipolar transistor 12. This can lead to problems of degradation of the transistor 12 and, accordingly, the entire buffer, when enabled as the transistor 12 can become reverse-biased during a high-to-low transition of the node 10.
While undesirable reverse-biasing of the transistor 12 can occur when the buffer is enabled, such a situation is transient. More severe non-transient reverse-biasing (and forward-biasing) can occur when the buffer is disabled. The driver 16 drives the node 10 when operating in a transmitter mode. The receiver buffer is disabled at this time and the connection between the emitter of the transistor 12 and the node 10 makes the output stage subject to the output of the external driver.
The imposition of substantial reverse bias voltage (V.sub.BE &lt;0) between the base and emitter of the transistor 12 can produce a slow degradation and effect the long-term reliability of the chip. Furthermore, forward biasing of the output transistor can induce unintended current flow within the disabled buffer, hampering its effective operation.